In the server world, you need a super CPU, but with the increase of cores, the way of crystal data transmission has become more important. Recently, ARM announced a new CMN-600 (consistency grid network) interconnection bus with better performance, which is upgraded from the CCN-500 series.

The idea behind the consistency grid network is that you can put a bunch of CPU clusters (such as four 4 x A53) into a single crystal, and each part of the SoC needs to work together. The previous generation interconnection bus CCN-512 can support 12 plexes and 48 cores, while the new CMN-600 can support up to 128 cores (32 plexes, 4 cores per plex).

ARM also adds a new I/O device system cache mechanism, which can directly locate the memory and cache to the three-level cache without going through the CPU core, greatly reducing latency. In addition, a new memory controller DMC-620 was released, replacing the previous DMC-520 (limited to four channel DDR3). The DMC-600 controller supports eight channel DDR4, with a maximum capacity of 1TB DDR4 per channel, totaling 8TB.

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