While welcoming the arrival of Snapdragon 820, ARM also released a new architecture for embedded devices and IoT (Internet of Things) - Cortex-A32.

With its excellent energy consumption ratio, ARM based processors have always occupied the mobile/embedded device market. It is well-known because of the explosion of smart phones. Generation CPU architectures such as A8/A9/A15, A12/A53/A57/A72 are also the imprint of the times in the minds of mobile friends. And the A32 just released has gone further and further in terms of efficiency ratio.

ARM's genealogy and positioning

The Cortex-A series is divided into three categories: high performance, low power consumption and ultra-low power consumption:

• The representatives of high-performance series are of course the large core architectures of ARM, Cortex A57 and A72 (as well as A15 and A17, which are slowly delisting);

• The low power consumption series is represented by the high performance ratio A53. According to the demand, it can use multi-core, or big LITTLE works in the form of large and small cores;

• The ultra-low power consumption series, after A5 and A7, includes the A35 launched in November 2015 and the A32 just launched.

We analyzed the A35 when it came out. You can check the article on the right:《 》。

It is worth noting that A32 is the only 32-bit architecture in the new generation architecture of ARM. But the A32 is like the 32-bit version of the A35. The goal is clear, which is to further control the power consumption based on the performance of the A35, which is already against the sky.

Ultra low power consumption and ultra small chip area

A32 framework diagram

The main chip area, power control and power consumption ratio of A32 architecture remain at 32 bits (ARMv7-A instruction set). The instruction prefetching unit is redesigned for efficiency. The first and second level cache, floating point and DSP operation performance are improved for speed, and new power management features are introduced. It supports TrustZone security encryption, NEON SIMD instruction set, DSP/SIMD extension, VFPv4 floating point computing, hardware virtualization, etc.

A32 can be manufactured by 28nm, 40nm and other processes according to the requirements, and the number of cores can be combined between 1/2/4 cores to form a big The SoC of LITTLE size core structure.

Schematic diagram of core size of A35, A32 can be even smaller

In the extreme case, the simplest version of single core plus 8KB level 1 cache can control the chip area to 0.25 mm2 (the A35 limit is only 0.4 mm2). The official said that the power consumption of the version manufactured with 28nm technology is only 0.004W (4mW) at 100MHz.

Efficiency ratio improved again

Performance comparison chart of integer, floating point, encryption and streaming media (encryption performance is 12 times better than A5)

Performance vs. power consumption

In addition to the ultra small chip area and energy consumption, the A32 can provide the same performance as the A35 in 32-bit. However, its lower power consumption makes its efficiency ratio (performance per unit power output) 10% higher than A35, 30% higher than A5 and 25% higher than A7. The A35 can achieve 80-100% performance of the A53 by increasing the frequency, that is, the A32 can also achieve the same performance level in 32-bit. At this time, the chip area is only 68% of the A53, and the power consumption is only 61% of the A53.

Under 64 bits, the A35 has the ability to replace the A53 architecture, while in 32 bits, the A32 is already a state of complete silence. Compared with the 64 bit A35 architecture, the 32-bit A32 is more suitable for wearable devices and Internet of Things products.

If the A35 is likely to be the first choice for the next generation of mobile phone processors, the A32 is already the "default solution" for the next generation of wearable devices and Internet of Things products.